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general description the ds3882 is a dual-channel cold-cathode fluorescent lamp (ccfl) controller for automotive applications that provides up to 300:1 dimming. it is ideal for driving ccfls used to backlight liquid crystal displays (lcds) in navigation and infotainment applications and for dri- ving ccfls used to backlight instrument clusters. the ds3882 is also appropriate for use in marine and avia- tion applications. the ds3882 features emi suppression functionality and provides a lamp current overdrive mode for rapid lamp heating in cold weather conditions. the ds3882 sup- ports configurations of 1 or 2 lamps with fully indepen- dent lamp control and minimal external components. multiple ds3882 controllers can be cascaded to sup- port applications requiring more than 2 lamps. control of the ds3882, after initial programming setup, can be completely achieved through i 2 c software communica- tion. many ds3882 functions are also pin-controllable if software control is not desired. applications automotive lcds instrument clusters marine and aviation lcds features ? dual-channel ccfl controllers for backlighting lcd panels and instrument clusters in automotive navigation/infotainment applications ? minimal external components required ? i 2 c interface ? per-channel lamp-fault monitoring for lamp- open, lamp-overcurrent, failure to strike, and overvoltage conditions ? status register reports fault conditions ? accurate (5%) independent on-board oscillators for lamp frequency (40khz to 100khz) and dpwm burst-dimming frequency (22.5hz to 440hz) ? lamp and dpwm frequencies can be synchronized with external sources to reduce visual lcd artifacts in video applications ? optional spread-spectrum lamp clock reduces emi ? lamp frequency can be stepped up or down to move emi spurs out of band ? lamp current overdrive mode with automatic turn-off quickly warms lamp in cold temperatures ? analog and digital brightness control ? 300:1 dimming range possible using the digital brightness control option ? programmable soft-start minimizes audible transformer noise ? on-board nonvolatile (nv) memory allows device customization ? 8-byte nv user memory for storage of serial numbers and date codes ? low-power standby mode ? 4.75v to 5.25v single-supply operation ? temperature range: -40c to +105c ? 28-pin tssop package ds3882 dual-channel automotive ccfl controller ______________________________________________ maxim integrated products 1 28 27 26 25 24 23 22 1 2 3 4 5 6 7 ovd2 lcm2 gb2 ga2 scl sda a0 fault top view v cc pdn lco bright losc 21 8 gnd psync 20 9 step posc 19 10 n.c. a1 18 11 ovd1 gnd_s 17 12 lcm1 svml 16 13 gb1 svmh 15 14 ga1 v cc lsync tssop ds3882 + pin configuration 19-5666; rev 2; 12/10 for pricing, delivery, and ordering information, please contact maxim direct at 1-888-629-4642, or visit maxim? website at www.maxim-ic.com. + denotes a lead(pb)-free/rohs-compliant package. t&r = tape and reel. ordering information typical operating circuit appears at end of data sheet. part temp range pin-package ds3882e+c -40c to +105c 28 tssop ds3882e+t&r/c -40c to +105c 28 tssop
ds3882 dual-channel automotive ccfl controller 2 _____________________________________________________________________ absolute maximum ratings recommended operating conditions (t a = -40? to +105?) stresses beyond those listed under ?bsolute maximum ratings?may cause permanent damage to the device. these are stress rating s only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specificatio ns is not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliability. voltage range on v cc , sda, and scl relative to ground.....................................-0.5v to +6.0v voltage range on leads other than v cc , sda, and scl ......................-0.5v to (v cc + 0.5v), not to exceed +6.0v continuous power dissipation (t a = +70?) tssop (derate 12.8mw/? above +70?) .............1025.6mw operating temperature range .........................-40? to +105? eeprom programming temperature range .........0? to +85? storage temperature range .............................-55? to +125? lead temperature (soldering, 10s) .................................+300? soldering temperature (reflow) .......................................+260? parameter symbol conditions min typ max units supply voltage v cc (note 1) 4.75 5.25 v input logic 1 v ih 2.0 v cc + 0.3 v input logic 0 v il -0.3 1.0 v svml/h voltage range v svm -0.3 v cc + 0.3 v bright voltage range v bright -0.3 v cc + 0.3 v lcm voltage range v lcm (note 2) -0.3 v cc + 0.3 v ovd voltage range v ovd (note 2) -0.3 v cc + 0.3 v gate-driver output charge loading q g 20 nc electrical characteristics (v cc = +4.75v to +5.25v, t a = -40? to +105?.) parameter symbol conditions min typ max units supply current i cc g a , g b l oad ed w i th 600p f, 2 channel s acti ve 12 ma input leakage (digital pins) i l -1.0 +1.0 ? power-down current i pdn 2ma output leakage (sda, fault )i lo high impedance -1.0 +1.0 ? low-level output voltage (lsync, psync) v ol i ol = 4ma 0.4 v v ol1 i ol1 = 3ma 0.4 low-level output voltage (sda, fault ) v ol2 i ol2 = 6ma 0.6 v low-level output voltage (ga, gb) v ol3 i ol3 = 4ma 0.4 v high-level output voltage (lsync, psync) v oh i oh = -1ma 2.4 v
ds3882 dual-channel automotive ccfl controller _____________________________________________________________________ 3 electrical characteristics (continued) (v cc = +4.75v to +5.25v, t a = -40? to +105?.) parameter symbol conditions min typ max units high-level output voltage (ga, gb) v oh1 i oh1 = -1ma v cc - 0.4 v uvlo threshold: v cc rising v uvlor 4.3 v uvlo threshold: v cc falling v uvlof 3.7 v uvlo hysteresis v uvloh 200 mv svml/h threshold: rising v svmr 2.03 2.08 2.15 v svml/h threshold: falling v svmf 1.95 2.02 2.07 v lcm and ovd dc bias voltage v dcb 1.1 v lcm and ovd input resistance r dcb 50 k lamp off threshold v lot (note 3) 0.22 0.25 0.28 v lamp over current v loc (note 3) 2.2 2.5 2.8 v lamp regulation threshold v lrt (notes 3, 4) 0.9 1.0 1.1 v ovd threshold v ovdt (note 3) 0.9 1.0 1.1 v lamp frequency source frequency range f lfs:osc 40 100 khz lamp frequency source frequency tolerance f lfs:tol losc resistor ?% over temperature -5 +5 % lamp frequency receiver frequency range f lfr:osc 40 100 khz lamp frequency receiver duty cycle f lfr:duty 40 60 % dpwm source (resistor) frequency range f dsr:osc 22.5 440.0 hz dpwm source (resistor) frequency tolerance f dsr:tol posc resistor ?% over temperature -5 +5 % dpwm source (ext. clk) frequency range f dse:osc 22.5 440.0 hz dpwm source (ext. clk) duty cycle f dfe:duty 40 60 % dpwm receiver min pulse width t dr:min (note 5) 25 ? bright voltage: minimum brightness v bmin 0.5 v bright voltage: maximum brightness v bmax 2.0 v gate driver output rise/fall time t r / t f c l = 600pf 100 ns gan and gbn duty cycle (note 6) 44 %
ds3882 dual-channel automotive ccfl controller 4 _____________________________________________________________________ note 1: all voltages are referenced to ground unless otherwise noted. currents into the ic are positive, out of the ic negative. note 2: during fault conditions, the ac-coupled feedback values are allowed to be below the absolute max rating of the lcm or ovd pin for up to 1 second. note 3: voltage with respect to v dcb . note 4: lamp overdrive and analog dimming (based on reduction of lamp current) are disabled. note 5: this is the minimum pulse width guaranteed to generate an output burst, which generates the ds3882? minimum burst duty cycle. this duty cycle may be greater than the duty cycle of the psync input. once the duty cycle of the psync input is greater than the ds3882? minimum duty cycle, the output? duty cycle tracks the psync? duty cycle. leaving psync low (0% duty cycle) disables the gan and gbn outputs in dpwm receiver mode. note 6: this is the maximum lamp frequency duty cycle that is generated at any of the gan or gbn outputs with spread-spectrum modulation disabled. note 7: i 2 c interface timing shown is for fast-mode (400khz) operation. this device is also backward compatible with i 2 c stan- dard-mode timing. note 8: after this period, the first clock pulse can be generated. note 9: c b ?otal capacitance allowed on one bus line in picofarads. note 10: eeprom write time applies to all the eeprom memory. eeprom write begins after a stop condition occurs. note 11: guaranteed by design. i 2 c ac electrical characteristics (see figure 9) (v cc = +4.75v to +5.25v, t a = -40? to +105?, timing referenced to v il(max) and v ih(min) .) parameter symbol conditions min typ max units scl clock frequency f scl (note 7) 0 400 khz bus free time between stop and start conditions t buf 1.3 ? hold time (repeated) start condition t hd:sta (note 8) 0.6 ? low period of scl t low 1.3 ? high period of scl t high 0.6 ? data hold time t hd:dat 0 0.9 ? data setup time t su:dat 100 ns start setup time t su:sta 0.6 ? sda and scl rise time t r (note 9) 20+ 0.1c b 300 ns sda and scl fall time t f (note 9) 20+ 0.1c b 300 ns stop setup time t su:sto 0.6 ? sda and scl capacitive loading c b (note 9) 400 pf eeprom write time t w (note 10) 20 30 ms nonvolatile memory characteristics (v cc = +4.75v to 5.25v) parameter symbol conditions min typ max units eeprom write cycles +85? (note 11) 30,000
ds3882 dual-channel automotive ccfl controller _____________________________________________________________________ 5 active supply current vs. supply voltage ds3882 toc01 supply voltage (v) supply current (ma) 5.20 5.15 4.80 4.85 4.90 5.00 5.05 4.95 5.10 4.5 5.0 5.5 6.0 6.5 7.0 7.5 8.0 4.0 4.75 5.25 dpwm = 10% dpwm = 50% dpwm = 100% svml< 2v f lf:osc = 64khz gate q c = 3.5nc active supply current vs. temperature ds3882 toc02 temperature ( c) supply current (ma) 32.5 5.7 5.9 6.1 6.3 6.5 6.7 6.9 7.1 7.3 7.5 5.5 -40.0 105 v cc = 4.75v v cc = 5.0v v cc = 5.25v dpwm = 100% f lf:osc = 64khz gate q c = 3.5nc internal frequency change vs. temperature ds3882 toc03 temperature ( c) frequency change (%) 32.5 -0.8 -0.6 -0.4 -0.2 0 0.2 0.4 0.6 0.8 1.0 -1.0 -40.0 10 5 dpwm frequency lamp frequency typical operation at 11v ds3882 toc04 10 s 5.0v g a 10 s 5.0v g b 10 s 2.00v lcm 10 s 2.00v ovd typical operation at 13v ds3882 toc05 10 s 5.0v g a 10 s 5.0v g b 10 s 2.00v lcm 10 s 2.00v ovd typical operation at 16v ds3882 toc06 10 s 5.0v g a 10 s 5.0v g b 10 s 2.00v lcm 10 s 2.00v ovd typical startup with svm ds3882 toc07 2ms 5.0v svml 2ms 5.0v g b 2ms 2.00v lcm 2ms 2.00v ovd burst dimming at 150hz and 10% ds3882 toc08 1ms 5.0v g a 1ms 5.0v g b 1ms 2.00v lcm 1ms 2.00v ovd burst dimming at 150hz and 50% ds3882 toc09 1ms 5.0v g a 1ms 5.0v g b 1ms 2.00v lcm 1ms 2.00v ovd typical operating characteristics (v cc = 5.0v, t a = +25?, unless otherwise noted.)
ds3882 dual-channel automotive ccfl controller 6 _____________________________________________________________________ typical operating characteristics (continued) (v cc = 5.0v, t a = +25?, unless otherwise noted.) soft-start at v inv = 16v ds3882 toc10 50 s 5.0v g a 50 s 5.0v g b 50 s 2.00v lcm 50 s 2.00v ovd lamp strike?xpanded view ds3882 toc11 1ms 5.0v g a 1ms 5.0v g b 1ms 2.00v lcm 1ms 2.00v ovd auto retry disabled ds3882 toc12 0.5s 5.0v g a 0.5s 5.0v g b 0.5s 2.00v lcm 0.5s 2.00 ovd staggered burst dimming start ds3882 toc13 0.2ms 2.00v ga1 0.2ms 2.00v ga2 autoretry disabled ds3882 toc14 0.1s 5.0v g a 0.1s 5.0v g b 0.1s 2.00v lcm 0.1s 2.00v ovd lamp opened
ds3882 dual-channel automotive ccfl controller _____________________________________________________________________ 7 pin description pins by channel (n) function name ch 1 ch 2 gan 15 25 mosfet a gate drive. connect directly to logic-level mode n-channel mosfet. leave open if channel is unused. gbn 16 26 mosfet b gate drive. connect directly to logic-level mode n-channel mosfet. leave open if channel is unused. lcmn 17 27 lamp current monitor input. lamp current is monitored by a resistor placed in series with the low-voltage side of the lamp. leave open if channel is unused. ovdn 18 28 overvoltage detection. lamp voltage is monitored by a capacitor divider placed on the high-voltage side of the transformer. leave open if channel is unused. name pin function fault alft a a a l l lft l laa t au t
ds3882 dual-channel automotive ccfl controller 8 _____________________________________________________________________ pin description (continued) name pin function posc 9 dpwm oscillator resistor adjust. a resistor to ground on this lead sets the frequency of the dpwm oscillator. this lead can optionally accept a 22.5hz to 440hz clock that will become the source timing of the internal dpwm signal. a1 10 address select input. determines i 2 c slave address. gnd_s 11 i 2 c interface ground connection. gnd_s must be at the same potential as gnd. svml 12 low-supply voltage monitor input. used to monitor the inverter voltage for undervoltage conditions. svmh 13 high-supply voltage monitor input. used to monitor the inverter voltage for overvoltage conditions. v cc 14, 24 power-supply connections. both pins must be connected. n.c. 19 no connection. do not connect any signal to this pin. step 20 lamp frequency step input. this active-high digital input moves the lamp oscillator frequency up or down by 1%, 2%, 3%, or 4% as configured in the emic register. this pin is logically ored with the stepe bit in the emic register. gnd 21 ground connection lco 22 lamp current overdrive enable input. a high digital level at this input enables the lamp current overdrive circuit. the amount of overdrive current is configured by the lcoc register. when this input is low, the lamp current is set to its nominal level. this pin is logically ored with the lcoe bit in the lcoc register. pdn 23 lamp on/off control input. a low digital level at this input turns the lamp on. a high digital level turns the lamps off, clears the fault logic, and places the device into the power-down mode. the high-to-low transition on this input issues a controller reset, which clears the fault logic and reinitiates a lamp strike. this pin is logically ored with the pdne bit in the cr2 register.
ds3882 dual-channel automotive ccfl controller _____________________________________________________________________ 9 functional diagrams gan mosfet gate drivers gbn ovdn overvoltage detection lamp frequency input/output [20.48mhz ~ 51.20mhz] i 2 c device configuration and control port 22.5hz to 440hz external resistor lamp frequency set gnd two independent ccfl controllers external resistor dpwm frequency set/dpwm clock input dpwm signal input/output analog brightness control svmh supply voltage monitor?igh [40khz ~ 100khz] system enable / por eeprom 8 byte user memory control registers fault channel fault channel enable sda scl lsync losc psync bright dpwm signal 2.0v status registers pdn lco 2.0v svml supply voltage monitor?ow step step lamp frequency up or down 40khz to 100khz oscillator ( 5%) lcmn lamp current monitor v cc [4.75v to 5.25v] x512 pll i 2 c interface system enable/ por fault handling 22.5hz to 440hz oscillator ( 5%) posc a0/a1 gnd_s dpss bit at cr1.3 lfss bit at cr1.2 uvlo vref mux poscs bit at cr1.1 mux rgso bit at cr1.4 mux dpss bit at cr1.3 ramp generator ds3882 figure 1. functional diagram
detailed description the ds3882 uses a push-pull drive scheme to convert a dc voltage (8v to 16v) to the high-voltage (300v rms to 1000v rms ) ac waveform that is required to power the ccfls. the push-pull drive scheme uses a minimal number of external components, which reduces assem- bly cost and makes the printed circuit board design easy to implement. the push-pull drive scheme also provides an efficient dc-to-ac conversion and pro- duces near-sinusoidal waveforms. each ds3882 channel drives two logic-level n-channel mosfets that are connected between the ends of a step-up transformer and ground (see the typical operating circuit ). the transformer has a center tap on the primary side that is connected to a dc voltage sup- ply. the ds3882 alternately turns on the two mosfets to create the high-voltage ac waveform on the sec- ondary side. by varying the duration of the mosfet turn-on times, the ccfl current is able to be accurately controlled. a resistor in series with the ccfl? ground connection enables current monitoring. the voltage across this resistor is fed to the lamp current monitor (lcm) input and compared to an internal reference voltage to deter- mine the duty cycle for the mosfet gates. each ccfl receives independent current monitoring and control, which maximizes the lamp? brightness and lifetime. block diagrams of the ds3882 are shown in figures 1 and 2. more operating details of the ds3882 are dis- cussed on the following pages of this data sheet. memory registers and i 2 c-compatible serial interface the ds3882 uses an i 2 c-compatible serial interface for communication with the on-board eeprom and sram configuration/status registers as well as user memory. the configuration registers, which are a mixture of shadowed eeprom and sram, allow the user to cus- tomize many ds3882 parameters such as the soft-start ramp rate, the lamp and dimming frequency sources, brightness of the lamps, fault-monitoring options, chan- nel enabling/disabling, emi control, and lamp current overdrive control. the eight bytes of nv user memory can be used to store manufacturing data such as date codes, serial numbers, or product identification num- bers. the device is shipped from the factory with the configuration registers programmed to a set of default configuration parameters. to inquire about custom pro- gramming, contact the factory. ds3882 dual-channel automotive ccfl controller 10 ____________________________________________________________________ gate drivers mosfet gate drivers gan gbn digital ccfl controller channel fault 512 x lamp frequency [20.48mhz ~ 51.20mhz] lamp frequency [40khz ~ 80khz] dimming pwm signal channel enable v lrt (1.0v nominal) lcmn lamp current monitor 300mv 2.5v lamp overcurrent lamp strike and regulation loce bit in cr1.0 lamp out 1.0v ovdn overvoltage detector lamp maximum voltage regulation 64 lamp cycle integrator overvoltage figure 2. per channel logic diagram functional diagrams (continued)
shadowed eeprom the ds3882 incorporates sram-shadowed eeprom memory locations for all memory that needs to be retained during power cycling. at power-up, seeb (bit 7 of the blc register) is low which causes the shadowed locations to act as ordinary eeprom. setting seeb high disables the eeprom write function and causes the shadowed locations to function as ordinary sram cells. this allows an infinite number of write cycles with- out causing eeprom damage and also eliminates the eeprom write time, t w from the write cycle. because memory changes made when seeb is set high are not written to eeprom, these changes are not retained through power cycles, and the power-up eeprom values are the last values written with seeb low. channel phasing the lamp-frequency mosfet gate turn-on times are out of phase between the two channels during the burst period. this reduces the inrush current that would result from all lamps switching simultaneously, and hence eases the design requirements for the dc sup- ply. it is important to note that it is the lamp-frequency signals that are phased, not the dpwm (burst) signals. lamp dimming control the ds3882 provides two independent methods of lamp dimming that can be combined to achieve a dim- ming ratio of 300:1 or greater. the first method is ?urst?dimming, which uses a digital pulse-width-mod- ulated (dpwm) signal (22.5hz to 440hz) to control the lamp brightness. the second is ?nalog?dimming, which is accomplished by adjusting the lamp current. burst dimming provides 128 linearly spaced brightness steps. analog dimming provides smaller substeps that allow incremental brightness changes between burst dimming steps. this ability is especially useful for low- brightness dimming changes, where using burst dim- ming alone would cause visible brightness step changes. analog dimming also allows the brightness to be reduced below the minimum burst dimming level, which provides for the maximum dimming range. burst dimming can be controlled using a user-supplied analog voltage on the bright pin or through the i 2 c interface. analog dimming can only be controlled through the i 2 c interface. therefore, for applications that require the complete dimming range and resolution capa- bility of the ds3882, i 2 c dimming control must be used. burst dimming burst dimming increases/decreases the brightness by adjusting (i.e., modulating) the duty cycle of the dpwm signal. during the high period of the dpwm cycle, the lamps are driven at the selected lamp frequency (40khz to 100khz) as shown in figure 6. this part of the cycle is called the ?urst?period because of the lamp frequency burst that occurs during this time. during the low period of the dpwm cycle, the controller disables the mosfet gate drivers so the lamps are not driven. this causes the current to stop flowing in the lamps, but the time is short enough to keep the lamps from de-ionizing. the ds3882 can generate its own dpwm signal inter- nally (set dpss = 0 in cr1), which can then be sourced to other ds3882s if required, or the dpwm sig- nal can be supplied from an external source (set dpss = 1 in cr1). to generate the dpwm signal internally, the ds3882 requires a clock (referred to as the dim- ming clock) to set the dpwm frequency. the user can supply the dimming clock by setting poscs = 1 in cr1 and applying an external 22.5hz to 440hz signal at the posc pin, or the dimming clock can be generated by the ds3882? internal oscillator (set poscs = 0 in cr1), in which case the frequency is set by an external resistor at the posc pin. these two dimming clock options are shown in figure 3. regardless of whether the dimming clock is generated internally or sourced externally, the poscr0 and poscr1 bits in cr2 must be set to match the desired dimming clock frequency. the internally generated dpwm signal can be provided at the psync i/o pin (set rgso = 0 in cr1) for sourc- ing to other ds3882s, if any, in the circuit. this allows all ds3882s in the system to be synchronized to the same dpwm signal. a ds3882 that is generating the dpwm signal for other ds3882s in the system is referred to as the dpwm source. when bringing in an externally generated dpwm signal, either from another ds3882 acting as a dpwm source or from some other user-provided source, it is input into the psync i/o pin of the ds3882, and the receiving ds3882 is referred to a dpwm receiver. in this mode, the bright and posc inputs are disabled and should be grounded (see figure 5). when the dpwm signal is generated internally, its duty cycle (and, thus, the lamp brightness) is controlled either by a user-supplied analog voltage at the bright input or through the i 2 c interface by varying the 7-bit pwm code in the bpwm register. when using the bright pin to control burst dimming, a voltage of less than 0.5v causes the ds3882 to operate with the mini- mum burst duty cycle, providing the lowest brightness setting, while any voltage greater than 2.0v causes a 100% burst duty cycle (i.e., lamps always being dri- ven), which provides the maximum brightness. for voltages between 0.5v and 2v, the duty cycle varies linearly between the minimum and 100%. writing a ds3882 dual-channel automotive ccfl controller ____________________________________________________________________ 11
ds3882 non-zero pwm code to the bpwm register disables the bright pin and enables i 2 c burst dimming control. setting the 7-bit pwm code to 0000001b causes the ds3882 to operate with the minimum burst duty cycle, while a setting of 1111111b causes a 100% burst duty cycle. for settings between these two codes, the duty cycle varies linearly between the minimum and 100%. analog dimming analog dimming changes the brightness by increasing or decreasing the lamp current. the ds3882 accom- plishes this by making small shifts to the lamp regula- tion voltage, v lrt (see figure 2). analog dimming is only possible by software communication with the lower five bits (lc4?c0) in the blc register. this function is not pin controllable. the default power-on state of the lc bits is 00000b, which corresponds to 100% of the nominal current level. therefore on power-up, analog dimming does not interfere with burst dimming func- tionality if it is not desired. setting the lc bits to 11111b reduces the lamp current to 35% of its nominal level. for lc values between 11111b and 00000b, the lamp cur- rent varies linearly between 35% and 100% of nominal. lamp frequency configuration the ds3882 can generate its own lamp frequency clock internally (set lfss = 0 in cr1), which can then be sourced to other ds3882s if required, or the lamp clock can be supplied from an external source (set lfss = 1 in cr1). when the lamp clock is internally generated, the frequency (40khz to 100khz) is set by an external resistor at the losc. in this case, the ds3882 can act as a lamp frequency source because the lamp clock is output at the lsync i/o pin for synchronizing any other ds3882s configured as lamp frequency receivers. while ds3882 is sourcing lamp frequency to other ds3882? and spread-spectrum modulation or frequency step features are enabled, the lsync output is not affected by either emi suppression features. the ds3882 acts as a lamp frequency receiv- er when the lamp clock is supplied externally. in this case, a 40khz to 100khz clock must be supplied at the lsync i/o. the external clock can originate from the lsync i/o of a ds3882 configured as a lamp frequency source or from some other source. dual-channel automotive ccfl controller 12 ____________________________________________________________________ bright psync posc 2.0v 0.5v 22.5hz to 440hz external resistor sets dpwm rate dpwm signal analog dimming control voltage resistor-set dimming clock bright psync posc 2.0v 0.5v 22.5hz to 440hz 22.5hz to 440hz dpwm signal external dpwm clock analog dimming control voltage external dimming clock figure 3. dpwm source configuration options bright psync posc 22.5hz to 440hz dpwm signal dpwm receiver figure 4. dpwm receiver configuration
ds3882 dual-channel automotive ccfl controller ____________________________________________________________________ 13 2.0v bright lamp frequency source dpwm source psync lsync posc losc 0.5v resistor-set dimming frequency resistor-set lamp frequency ds3882 bright lamp frequency receiver dpwm receiver psync lsync posc losc ds3882 2.0v bright lamp frequency source dpwm source psync lsync posc losc 0.5v analog brightness analog brightness resistor-set lamp frequency dimming clock (22.5hz to 440hz) dpwm signal (22.5hz to 440hz) ds3882 bright lamp frequency receiver dpwm receiver psync lsync posc losc ds3882 bright lamp frequency source dpwm receiver psync lsync posc losc resistor-set lamp frequency ds3882 bright lamp frequency receiver dpwm receiver psync lsync posc losc ds3882 2.0v bright lamp frequency receiver dpwm source psync lsync posc losc n.c. n.c. n.c. n.c. n.c. n.c. n.c. n.c. n.c. n.c. n.c. n.c. n.c. n.c. n.c. n.c. n.c. 0.5v resistor-set dimming frequency ds3882 bright lamp frequency receiver dpwm receiver psync lsync posc losc ds3882 2.0v bright lamp frequency receiver dpwm source psync lsync posc losc 0.5v analog brightness analog brightness lamp clock (40khz to 100khz) dimming clock (22.5hz to 440hz) lamp clock (40khz to 100khz) dpwm signal (22.5hz to 440hz) lamp clock (40khz to 100khz) ds3882 bright lamp frequency receiver dpwm receiver psync lsync posc losc ds3882 bright lamp frequency receiver dpwm receiver psync lsync posc losc ds3882 bright lamp frequency receiver dpwm receiver psync lsync posc losc ds3882 figure 5. frequency configuration options for designs using multiple ds3882s
ds3882 dual-channel automotive ccfl controller 14 ____________________________________________________________________ configuring systems with multiple ds3882s the source and receiver options for the lamp frequency clock and dpwm signal allow multiple ds3882s to be synchronized in systems requiring more than two lamps. the lamp and dimming clocks can either be generated on board the ds3882 using external resis- tors to set the frequency, or they can be sourced by the host system to synchronize the ds3882 to other system resources. figure 5 shows various multiple ds3882 configurations that allow both lamp and/or dpwm syn- chronization for all ds3882s in the system. dpwm soft-start at the beginning of each lamp burst, the ds3882 pro- vides a soft-start that slowly increases the mosfet gate-driver duty cycle (see figure 6). this minimizes the possibility of audible transformer noise that could result from current surges in the transformer primary. the soft-start length is fixed at 16 lamp cycles, but the soft-start ramp profile is programmable through the four soft-start profile registers (ssp1/2/3/4) and can be adjusted to match the application. there are seven dif- ferent driver duty cycles to select from to customize the soft-start ramp (see tables 5a and 5b). the available duty cycles range from 0% to 19% in ~3% increments. in addition, the mosfet duty cycle from the last lamp cycle of the previous burst can be used as part of the soft-start ramp by using the most recent value duty cycle code. each programmed mosfet gate duty cycle repeats twice to make up the 16 soft-start lamp cycles. 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 ssp1. 0-3 lamp current soft-start profile register soft-start soft-start (expanded) 22.5hz to 440hz dpwm signal lamp current lamp cycle gan/gbn mosfet gate drivers programmable soft-start profile with increasing mosfet pulse widths over a 16 lamp cycle period results in a linear ramp in lamp current. ssp1. 4-7 ssp2. 0-3 ssp2. 4-7 ssp3. 0-3 ssp3. 4-7 ssp4. 0-3 ssp4. 4-7 1 figure 6. digital pwm dimming and soft-start
setting the lamp and dimming clock (dpwm) frequencies using external resistors both the lamp and dimming clock frequencies can be set using external resistors. the resistance required for either frequency can be determined using the following formula: where k = 1600k ? khz for lamp frequency calculations. when calculating the resistor value for the dimming clock frequency, k will be one of four values as determined by the desired frequency and the poscr0 and poscr1 bit settings as shown in the control register 2 (cr2) table 7 in the detailed register descriptions section. example: selecting the resistor values to configure a ds3882 to have a 50khz lamp frequency and a 160hz dimming clock frequency: for this configuration, poscr0 and poscr1 must be programmed to 1 and 0, respectively, to select 90hz to 220hz as the dimming clock frequency range. this sets k for the dimming clock resistor (r posc ) calculation to 4k ? khz. for the lamp frequency resistor (r losc ) calculation, k = 1600k ? khz, which sets the lamp frequency k value regardless of the frequency. the formula above can now be used to calculate the resistor values for r losc and r posc as follows: supply monitoring the ds3882 has supply voltage monitors (svms) for both the inverter? transformer dc supply (v inv ) and its own v cc supply to ensure that both voltage levels are adequate for proper operation. the transformer supply is monitored for overvoltage conditions at the svmh pin and undervoltage conditions at the svml pin. external resistor-dividers at each svm input feed into two com- parators (see figure 7), both having 2v thresholds. using the equation below to determine the resistor val- ues, the svmh and svml trip points (v trip ) can be customized to shut off the inverter when the trans- former? supply voltage rises above or drops below specified values. operating with the transformer? sup- ply at too low of a level can prevent the inverter from reaching the strike voltage and could potentially cause numerous other problems. operating with the trans- former voltage at too high of a level can be damaging to the inverter components. proper use of the svms can prevent these problems. if desired, the high and/or low svms can be disabled by connecting the svmh pin to gnd and the svml pin to v cc . the v cc monitor is used as a 5v supply undervoltage lockout (uvlo) that prevents operation when the ds3882 does not have adequate voltage for its analog circuitry to operate or to drive the external mosfets. the v cc monitor features hysteresis to prevent v cc noise from causing spurious operation when v cc is near the trip point. this monitor cannot be disabled by any means. fault monitoring the ds3882 provides extensive fault monitoring for each channel. it can detect open-lamp, lamp overcur- rent, failure to strike, and overvoltage conditions. the ds3882 can be configured to disable all channels if one or more channels enter a fault state or it can be configured to disable only the channel where the fault occurred. once a fault state has been entered, the fault output is asserted and the channel(s) remains disabled until it is reset by a user or host control event. see step 4, fault handling for more detail. the ds3882 can also be configured to automatically attempt to clear a detected fault (except lamp overcurrent) by re-striking the lamp. configuration bits for the fault monitoring options are located in cr1 and cr2. the ds3882 also has real-time status indicators bits located in the sr1 and sr2 register (sram) that assert whenever a corre- sponding fault occurs. v rr r trip . = ? ? ? ? ? ? + 20 12 1 r k khz khz k r k khz khz k losc posc . . . = ? = = ? = 1600 50 32 0 4 0 160 25 0 r k f osc osc = ds3882 dual-channel automotive ccfl controller ____________________________________________________________________ 15 svml r 2 r 1 2.0v v inv svmh r 2 v trip v trip r 1 2.0v v inv ds3882 figure 7. setting the svm threshold voltage
ds3882 figure 8 shows a flowchart of how the ds3882 controls and monitors each lamp. the steps are as follows: 1) supply check?he lamps do not turn on unless the ds3882 supply voltage is above 4.3v and the volt- age at the supply voltage monitors, svml and svmh, are respectively above 2.0v and below 2.0v. 2) strike lamp?hen both the ds3882 and the dc inverter supplies are at acceptable levels, the ds3882 attempts to strike each enabled lamp. the ds3882 slowly ramps up the mosfet gate duty cycle until the lamp strikes. the controller detects that the lamp has struck by detecting current flow in the lamp, detected by the lcmn pin. if during the strike ramp, the maximum allowable voltage is reached on the ovdn pin, the controller stops increasing the mosfet gate duty cycle to keep from overstressing the system. the ds3882 goes into a fault handling state (step 4) if the lamp has not struck after the timeout period as defined by the lst0 and lst1 control bits in the ssp1 register. if an overvolt- age event is detected during the strike attempt, the ds3882 disables the mosfet gate drivers and go into the fault handling state. 3) run lamp?nce the lamp is struck, the ds3882 adjusts the mosfet gate duty cycle to optimize the lamp current. the gate duty cycle is always con- strained to keep the system from exceeding the maximum allowable lamp voltage. the lamp current sampling rate is user-selectable using the lsr0 and lsr1 bits in cr2. if lamp current ever drops below the lamp out reference point for the period as defined by the lst0 and lst1 control bits in the ssp1 register, then the lamp is considered extinguished. in this case, the mosfet gate drivers are disabled and the device moves to the fault handling stage. 4) fault handling?uring fault handling, the ds3882 performs an optional (user-selectable) automatic retry to attempt to clear all faults except a lamp over- current. the automatic retry makes 14 additional attempts to rectify the fault before declaring the channel in a fault state and permanently disabling the channel. between each of the 14 attempts, the controller waits 1024 lamp cycles. in the case of a lamp overcurrent, the ds3882 instantaneously declares the channel to be in a fault state and per- manently disables the channel. the ds3882 can be configured to disable all channels if one or more channels enter a fault state or it can be configured to disable only the channel where the fault occurred. once a fault state is entered, the channel remains in that state until one of the following occurs: ? v cc drops below the uvlo threshold. ? the svml or svmh thresholds are crossed. ? the pdn pin goes high. ? the pdne software bit is written to a logic 1. ? the channel is disabled by the ch1d or ch2d control bit. dual-channel automotive ccfl controller 16 ____________________________________________________________________
ds3882 dual-channel automotive ccfl controller ____________________________________________________________________ 17 mosfet gate drivers enabled device and inverter supplies at proper levels? strike lamp [ramp and regulate to ovd threshold] fault wait [1024 lamp cycles] lamp strike timeout [see register ssp1] run lamp [regulate lamp current bounded by lamp voltage] lamp out timeout [see register ssp1] increment fault counter / set fault_rt status bit fault counter = 15? fault state [activate fault output] lamp overcurrent [instantaneous if enabled by the loce bit at cr1.0] no yes autoretry enabled? [ard bit at cr1.5] no yes yes overvoltage [64 lamp cycles] set lout_l status bit set ov_l status bit set sto_l status bit set loc_l status bit clear fault_rt status bit if lamp regulation threshold is met reset fault counter and fault output set fault_l and fault_rt status bits figure 8. fault-handling flowchart
ds3882 dual-channel automotive ccfl controller 18 ____________________________________________________________________ emi suppression functionality the ds3882 contains two electromagnetic interference suppression features: spread-spectrum modulation and lamp oscillator frequency stepping. the first is the abili- ty to spread the spectrum of the lamp frequency. by setting either ss0 and/or ss1 in emic register, the con- troller can be configured to dither the lamp frequency by ?.5%, ?%, or ?%. by setting a non-zero value in ss0/1, spread-spectrum modulation is enabled and oscillator frequency stepping is disabled. in spread- spectrum modulation mode the dither modulation rate is also selectable by setting fs0/1/2, and has either a triangular (ssm = 0) or a pseudorandom profile (ssm = 1). users have the flexibility to choosing the best modu- lation rate (through fs0/1/2) for the application. the second emi suppression scheme is the ability to move the lamp frequency up or down by 1%, 2%, 3%, or 4%. in this scheme, the actual radiated emi is not reduced but it is moved out of a sensitive frequency region. stepe bit and/or step pin is used to enable lamp frequency stepping (ss0/1 must be 0). once enabled, the fs0/1/2 value controls the lamp oscillator frequency shift. for example, if the lamp frequency cre- ates emi disturbing an audio radio station, it can be moved up or down slightly to slide the spurious interfer- er out of band. lamp current overdrive functionality another feature the ds3882 offers is the ability to over- drive the lamps to allow them to heat up quickly in cold environments. after setting the lco0/1/2 bits in the lcoc register and enabling the lcoe bit or lco pin, the ds3882 overdrives the nominal current settings in 12.5% steps from 112.5% up to 200%. the ds3882 accomplishes this by automatically shifting the lamp regulation threshold, v lrt , upward to allow more cur- rent to flow in the lamps (figure 2). this multilevel adjustment makes it possible to slowly decrease the current overdrive (through i 2 c) after the lamps have warmed up, so the end user does not see any change in brightness when the overdrive is no longer needed. the ds3882 also features an optional timer capable of automatically turning off the current overdrive. this timer is adjustable from approximately 1.5 minutes to 21 minutes (if a 50khz lamp frequency is used). detailed register descriptions the ds3882? register map is shown in table 1. detailed register and bit descriptions follow in the sub- sequent tables. table 1. register map byte address byte name factory default bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 e0h sr1 00h svmh_rt svml_rt loc_l1 lout_l1 ov_l1 sto_l1 fault_l1 fault_rt1 e1h sr2 00h rsvd rsvd loc_l1 lout_l2 ov_l2 sto_l2 fault_l2 fault_rt2 e2h bpwm 00h rsvd pwm6 pwm5 pwm4 pwm3 pwm2 pwm1 pwm0 e3h blc 1fh seeb ch2d ch1d lc4 lc3 lc2 lc1 lc0 f0h ssp1 21h lst1 mdc code for soft-start lamp cycles 3, 4 lst0 mdc code for soft-start lamp cycles 1, 2 f1h ssp2 43h mdc code for soft-start lamp cycles 7, 8 mdc code for soft-start lamp cycles 5, 6 f2h ssp3 65h mdc code for soft-start lamp cycles 11, 12 mdc code for soft-start lamp cycles 9, 10 f3h ssp4 77h mdc code for soft-start lamp cycles 15, 16 mdc code for soft-start lamp cycles 13, 14 f4h cr1 00h dpd frs ard rgso dpss lfss poscs loce f5h cr2 08h pdne rsvd rsvd lsr1 lsr0 poscr1 poscr0 umwp f6h emic 00h fs2 fs1 fs0 stepe rsvd ssm ss1 ss0 f7h lcoc 00h to3 to2 to1 to0 lcoe lco2 lco1 lco0 f8h?fh user 00h ee ee ee ee ee ee ee ee note 1: e0h?3h are sram locations, and f0h?fh are sram-shadowed eeprom. note 2: altering ds3882 configuration during active ccfl operation can cause serious adverse effects. note 3: the bpwm, blc, and lcoc registers control both channels of the ds3882.
ds3882 dual-channel automotive ccfl controller ____________________________________________________________________ 19 table 2. status register 1 (sr1) [sram, e0h] bit r/w power-up default name function 0 r 0 fault_rt fault condition?eal time. a real-time bit that indicates the current operating status of channel 1. 0 = normal condition 1 = fault condition 1 r 0 fault_l fault condition?atched. a latched bit that is set when the channel enters a fault condition. this bit is cleared when read, regardless of the current state of fault. 2 r 0 sto_l lamp strike timeout?atched. a latched bit that is set when the lamp fails to strike. this bit is cleared when read. 3 r 0 ov_l overvoltage?atched. a latched bit that is set when a lamp overvoltage is present for at least 64 lamp cycles. this bit is cleared when read. 4 r 0 lout_l lamp out?atched. a latched bit that is set when a lamp out is detected. this bit is cleared when read. 5 r 0 loc_l lamp overcurrent?atched. a latched bit that is set when a lamp overcurrent is detected. this bit is cleared when read. 6 r 0 svml_rt supply voltage monitor low?eal time. a real-time bit that reports the comparator output of the svml pin. 7 r 0 svmh_rt supply voltage monitor high?eal time. a real-time bit that reports the comparator output of the svmh pin. note 1: writing to this register has no effect on it. note 2: see figure 8 for more details on how the status bits are set. note 3: sr1 is cleared when any of the following occurs: ? v cc drops below the uvlo threshold ? the svml or svmh thresholds are crossed ? the pdn hardware pin goes high ? the pdne software bit is written to a logic 1 ? the channel is disabled by the ch1d control bit
ds3882 dual-channel automotive ccfl controller 20 ____________________________________________________________________ table 3. status register 2 (sr2) [sram, e1h] bit r/w power-up default name function 0 r 0 fault_rt fault condition?eal time. a real-time bit that indicates the current operating status of channel 2. 0 = normal condition 1 = fault condition 1 r 0 fault_l fault condition?atched. a latched bit that is set when the channel enters a fault condition. this bit is cleared when read regardless of the current state of fault. 2 r 0 sto_l lamp strike time out?atched. a latched bit that is set when the lamp fails to strike. this bit is cleared when read. 3 r 0 ov_l overvoltage?atched. a latched bit that is set when a lamp overvoltage is present for at least 64 lamp cycles. this bit is cleared when read. 4 r 0 lout_l lamp out?atched. a latched bit that is set when a lamp out is detected. this bit is cleared when read. 5 r 0 loc_l lamp overcurrent?atched. a latched bit that is set when a lamp overcurrent is detected. this bit is cleared when read. 6 r 0 rsvd reserved. could be either 0 or 1 when read. 7 r 0 rsvd reserved. could be either 0 or 1 when read. note 1: writing to this register has no effect on it. note 2: see figure 8 for more details on how the status bits are set. note 3: sr2 is cleared when any of the following occurs: ? v cc drops below the uvlo threshold ? the svml or svmh thresholds are crossed ? the pdn hardware pin goes high ? the pdne software bit is written to a logic 1 ? the channel is disabled by the ch2d control bit table 4. brightness lamp current register (blc) [sram, e3h] bit r/w factory default name function 0 r/w 0 lc0 1 r/w 0 lc1 2 r/w 0 lc2 3 r/w 0 lc3 4 r/w 0 lc4 these five control bits determine the target value for the lamp current. 11111b is 35% of the nominal level and 00000b is 100% of the nominal level. these control bits are used for fine adjustment of the lamp brightness. 5 r/w 0 ch1d channel 1 disable 0 = channel 1 enabled 1 = channel 1 disabled 6 r/w 0 ch2d channel 2 disable. useful for dimming in two lamp applications. 0 = channel 2 enabled 1 = channel 2 disabled 7 r/w 0 seeb sram-shadowed eeprom write control 0 = enables writes to eeprom 1 = disables writes to eeprom
ds3882 dual-channel automotive ccfl controller ____________________________________________________________________ 21 table 5a. soft-start protocol registers (sspx) [shadowed-eeprom, f0h, f1h, f2h, f3h] msb lsb ssp# addr factory default 7 654 3 2 1 0 ssp1 f0h 21h lst1 lamp cycles 3 and 4 lst0 lamp cycles 1 and 2 ssp2 f1h 43h rsvd lamp cycles 7 and 8 rsvd lamp cycles 5 and 6 ssp3 f2h 65h rsvd lamp cycles 11 and 12 rsvd lamp cycles 9 and 10 ssp4 f3h 77h rsvd lamp cycles 15 and 16 rsvd lamp cycles 13 and 14 table 5b. mosfet duty cycle (mdc) ? codes for soft-start settings bit r/w name function 0 r/w mdc0 mdc0/1/2: these bits determine a mosfet duty cycle that will repeat twice in the 16 lamp cycle soft-start. 1 r/w mdc1 mdc code mosfet duty cycle mdc code mosfet duty cycle 0h fixed at 0% 4h fixed at 13% 2 r/w mdc2 1h fixed at 3% 5h fixed at 16% 2h fixed at 6% 6h fixed at 19% 3h fixed at 9% 7h most recent value 3 r/w lst0 / rsvd 4 r/w mdc0 lst0/1: these bits select strike and lamp-out timeout. lst0 and lst1 control fault behavior for all lamps. 5 r/w mdc1 lst1 lst0 strike and lamp-out timeout (lamp frequency cycles) example timeout if lamp frequency is 50khz 0 0 32,768 0.66 seconds 6 r/w mdc2 0 1 65,536 1.31 seconds 1 0 98,304 1.97 seconds 7 r/w lst1 / rsvd 1 1 reserved
ds3882 dual-channel automotive ccfl controller 22 ____________________________________________________________________ table 6. control register 1 (cr1) [shadowed-eeprom, f4h] bit r/w factory default name function 0 r/w 0 loce lamp overcurrent enable 0 = lamp overcurrent detection disabled. 1 = lamp overcurrent detection enabled. 1 r/w 0 poscs posc select. see poscr0 and poscr1 control bits in control register 2 to select the oscillator range. 0 = posc input is connected with a resistor to ground to set the frequency of the internal pwm oscillator. 1 = posc input is a 22.5hz to 440hz clock. 2 r/w 0 lfss lamp frequency source select 0 = lamp frequency generated internally and sourced from the lsync output. 1 = lamp frequency generated externally and supplied to the lsync input. 3 r/w 0 dpss dpwm signal source select 0 = dpwm signal generated internally and sourced from the psync output. 1 = dpwm signal generated externally and supplied to the psync input. 4 r/w 0 rgso ramp generator source option 0 = source dpwm at the psync output. 1 = source internal ramp generator at the psync output. 5 r/w 0 ard autoretry disable 0 = autoretry function enabled. 1 = autoretry function disabled. 6 r/w 0 frs fault response select 0 = disable only the malfunctioning channel. 1 = disable both channels upon fault detection on any channel. 7 r/w 0 dpd dpwm disable 0 = dpwm function enabled. 1 = dpwm function disabled.
ds3882 dual-channel automotive ccfl controller ____________________________________________________________________ 23 table 7. control register 2 (cr2) [shadowed-eeprom, f5h] bit r/w default name function 0 r/w 0 umwp user memory write protect 0 = write access blocked. 1 = write access permitted. 1 r/w 0 poscr0 dpwm oscillator range select. when using an external source for the dimming clock, these bits must be set to match the external oscillator? frequency. when using a resistor to set the dimming frequency, these bits plus the external resistor control the frequency. poscr1 poscr0 dimming clock (dpwm) frequency range (hz) k (k ? khz) 0 0 22.5 to 55.0 1 0 1 45 to 110 2 1 0 90 to 220 4 2 r/w 0 poscr1 1 1 180 to 440 8 lamp sample rate select. determines the feedback sample rate of the lcm inputs. lsr1 lsr0 selected lamp sample rate example sample rate if lamp frequency is 50khz 3 r/w 1 lsr0 0 0 4 lamp frequency cycles 12,500hz 0 1 8 lamp frequency cycles 6,250hz 1 0 16 lamp frequency cycles 3,125hz 4 r/w 0 lsr1 1 1 32 lamp frequency cycles 1,563hz 5 0 rsvd reserved. this bit should be set to zero. 6 0 rsvd reserved. this bit should be set to zero. 7 r/w 0 pdne power-down. logically ored with the pdn pin. setting this bit high resets the controller, clears the fault logic, and places the part in power-down mode. 0 = normal. all circuitry is off, except i 2 c interface.
ds3882 dual-channel automotive ccfl controller 24 ____________________________________________________________________ table 8. emi control register (emic) [shadowed-eeprom, f6h] bit r/w factory default name function lamp oscillator spread-spectrum modulation select ss1 ss0 selected lamp frequency spread 0 r/w 0 ss0 0 0 spread-spectrum disabled 0 1 ?.5% 1 0 ?.0% 1 r/w 0 ss1 1 1 ?.0% 2 r/w 0 ssm lamp oscillator spread-spectrum modulation select 0 = triangular modulation. 1 = pseudorandom modulation. 3 ?? rsvd reserved. this bit should be set to zero. 4 r/w 0 stepe lamp frequency step enable. logically ored with the step invoked. 0 = lamp operates at nominal frequency. 1 = frequency step invoked. lamp oscillator frequency step select fs2 fs1 fs0 selected lamp frequency step (ss0 = 0 and ss1= 0) spread-spectrum modulation rate (ss0 and/or ss1 = 1) 5 r/w 0 fs0 0 0 0 step up 1% lamp frequency x4 0 0 1 step up 2% lamp frequency x2 0 1 0 step up 3% lamp frequency x1 0 1 1 step up 4% lamp frequency x1/2 6 r/w 0 fs1 1 0 0 step down 1% lamp frequency x1/4 1 0 1 step down 2% lamp frequency x1/8 1 1 0 step down 3% lamp frequency x1/16 7 r/w 0 fs2 1 1 1 step down 4% lamp frequency x1/32
ds3882 dual-channel automotive ccfl controller ____________________________________________________________________ 25 table 9. lamp current overdrive control register (lcoc) [shadowed-eeprom, f7h] bit r/w factory default name function lamp current overdrive select lco2 lco1 lco0 selected lamp current overdrive 0 0 0 nominal current + 12.50% 0 r/w 0 lco0 0 0 1 nominal current + 25.00% 0 1 0 nominal current + 37.50% 0 1 1 nominal current + 50.00% 1 r/w 0 lco1 1 0 0 nominal current + 62.50% 1 0 1 nominal current + 75.00% 1 1 0 nominal current + 87.50% 2 r/w 0 lco2 1 1 1 nominal current + 100.00% 3 r/w 0 lcoe lamp current overdrive enable. logically ored with the lco pin. 0 = lamp operated with nominal current setting. 1 = lamp overdrive invoked. automatic lamp current overdrive timeout select to3 to2 to1 to0 selected timeout in lamp frequency cycles example timeout if lamp frequency is 50khz 4 r/w 0 to0 0 0 0 0 disabled 00 01 1 x 2 22 1.4 min 00 10 2 x 2 22 2.8 min 00 11 3 x 2 22 4.2 min 01 00 4 x 2 22 5.6 min 5 r/w 0 to1 01 01 5 x 2 22 7.0 min 01 10 6 x 2 22 8.4 min 01 11 7 x 2 22 9.8 min 10 00 8 x 2 22 11.2 min 10 01 9 x 2 22 12.6 min 6 r/w 0 to2 1 0 1 0 10 x 2 22 14.0 min 1 0 1 1 11 x 2 22 15.4 min 1 1 0 0 12 x 2 22 16.8 min 1 1 0 1 13 x 2 22 18.2 min 1 1 1 0 14 x 2 22 19.6 min 7 r/w 0 to3 1 1 1 1 15 x 2 22 21.0 min
ds3882 dual-channel automotive ccfl controller 26 ____________________________________________________________________ i 2 c definitions the following terminology is commonly used to describe i 2 c data transfers: master device: the master device controls the slave devices on the bus. the master device generates scl clock pulses, start, and stop conditions. slave devices: slave devices send and receive data at the master? request. bus idle or not busy: time between stop and start conditions when both sda and scl are inactive and in their logic-high states. start condition: a start condition is generated by the master to initiate a new data transfer with a slave. transitioning sda from high to low while scl remains high generates a start condition. see the timing dia- gram for applicable timing. stop condition: a stop condition is generated by the master to end a data transfer with a slave. transitioning sda from low to high while scl remains high gener- ates a stop condition. see the timing diagram for applicable timing. repeated start condition: the master can use a repeated start condition at the end of one data transfer to indicate that it will immediately initiate a new data transfer following the current one. repeated starts are commonly used during read operations to identify a specific memory address to begin a data transfer. a repeated start condition is issued identically to a nor- mal start condition. see the timing diagram for applica- ble timing. bit write: transitions of sda must occur during the low state of scl. the data on sda must remain valid and unchanged during the entire high pulse of scl plus the setup and hold time requirements (see figure 9). data is shifted into the device during the rising edge of the scl. bit read: at the end of a write operation, the master must release the sda bus line for the proper amount of setup time (see figure 9) before the next rising edge of scl during a bit read. the device shifts out each bit of data on sda at the falling edge of the previous scl pulse and the data bit is valid at the rising edge of the current scl pulse. remember that the master gener- ates all scl clock pulses including when it is reading bits from the slave. acknowledgement (ack and nack): an acknowl- edgement (ack) or not acknowledge (nack) is always the 9th bit transmitted during a byte transfer. the device receiving data (the master during a read or the slave during a write operation) performs an ack by transmitting a zero during the 9th bit. a device per- forms a nack by transmitting a one during the 9th bit. timing (figure 9) for the ack and nack is identical to all other bit writes. an ack is the acknowledgment that the device is properly receiving data. a nack is used to terminate a read sequence or as an indication that the device is not receiving data. byte write: a byte write consists of 8 bits of informa- tion transferred from the master to the slave (most sig- nificant bit first) plus a 1-bit acknowledgement from the slave to the master. the 8 bits transmitted by the mas- ter are done according to the bit-write definition and the acknowledgement is read using the bit-read definition. sda scl t hd:sta t low t high t r t f t buf t hd:dat t su:dat repeated start t su:sta t hd:sta t su:sto t sp stop note: timing is reference to v il(max) and v ih(min) . start figure 9. i 2 c timing diagram
byte read: a byte read is an 8-bit information transfer from the slave to the master plus a 1-bit ack or nack from the master to the slave. the 8 bits of information that are transferred (most significant bit first) from the slave to the master are read by the master using the bit read definition above, and the master transmits an ack using the bit write definition to receive additional data bytes. the master must nack the last byte read to ter- minate communication so the slave will return control of sda to the master. slave address byte: each slave on the i 2 c bus responds to a slave addressing byte sent immediately following a start condition. the slave address byte (figure 10) contains the slave address in the most sig- nificant seven bits and the r/ w bit in the least signifi- cant bit. the ds3882? slave address is 10100a 1 a 0 0 (binary), where a 0 and a 1 are the values of the address pins (a0 and a1). the address pin allows the device to respond to one of four possible slave addresses. by writing the correct slave address with r/ w = 0, the master indicates it will write data to the slave. if r/ w = 1, the master will read data from the slave. if an incor- rect slave address is written, the ds3882 will assume the master is communicating with another i 2 c device and ignore the communications until the next start con- dition is sent. memory address: during an i 2 c write operation, the master must transmit a memory address to identify the memory location where the slave is to store the data. the memory address is always the second byte trans- mitted during a write operation following the slave address byte. i 2 c communication writing a data byte to a slave: the master must gen- erate a start condition, write the slave address byte (r/ w = 0), write the memory address, write the byte of data, and generate a stop condition. remember the master must read the slave? acknowledgement during all byte write operations. see figure 11 for more detail. acknowledge polling: any time eeprom is written, the ds3882 requires the eeprom write time (t w ) after the stop condition to write the contents to eeprom. during the eeprom write time, the ds3882 will not acknowledge its slave address because it is busy. it is possible to take advantage of that phenomenon by repeatedly addressing the ds3882, which allows the next byte of data to be written as soon as the ds3882 is ready to receive the data. the alternative to acknowl- edge polling is to wait for a maximum period of t w to elapse before attempting to write again to the ds3882. eeprom write cycles: the number of times the ds3882? eeprom can be written before it fails is specified in the nonvolatile memory characteristics table. this specification is shown at the worst-case write temperature. the ds3882 is typically capable of handling many additional write cycles when the writes are performed at room temperature. reading a data byte from a slave: to read a single byte from the slave the master generates a start condi- tion, writes the slave address byte with r/ w = 0, writes the memory address, generates a repeated start condi- tion, writes the slave address with r/ w = 1, reads the data byte with a nack to indicate the end of the trans- fer, and generates a stop condition. see figure 11 for more detail. ds3882 dual-channel automotive ccfl controller ____________________________________________________________________ 27 7-bit slave address most significant bit a 1, a 0 pin value determines read or write r/w 1 01 0 0a 1 a 0 figure 10. ds3882? slave address byte
ds3882 applications information addressing multiple ds3882s on a common i 2 c bus each ds3882 responds to one of four possible slave addresses based on the state of the address input pins (a0 and a1). for information about device addressing, see the i 2 c communication section. setting the rms lamp current resistor r7 and r8 in the typical operating circuit set the lamp current. r7 and r8 = 140 corresponds to a 5ma rms lamp current as long as the current waveform is approximately sinusoidal. the formula to determine the resistor value for a given sinusoidal lamp current is: component selection external component selection has a large impact on the overall system performance and cost. the two most important external components are the transformers and n-channel mosfets. the transformer should be able to operate in the 40khz to 80khz frequency range of the ds3882, and the turns ratio should be selected so the mosfet drivers run at 28% to 35% duty cycle during steady state operation. the transformer must be able to withstand the high open-circuit voltage that is used to strike the lamp. additionally, its primary/secondary resistance and induc- tance characteristics must be considered because they contribute significantly to determining the efficiency and transient response of the system. table 10 shows a transformer specification that has been used for a 12v inverter supply, 438mm x 2.2mm lamp design. the n-channel mosfet must have a threshold voltage that is low enough to work with logic-level signals, a low on-resistance to maximize efficiency and limit the n- channel mosfet? power dissipation, and a break- down voltage high enough to handle the transient. the breakdown voltage should be a minimum of 3x the invert- er voltage supply. additionally, the total gate charge must be less than q g , which is specified in the recommended operating conditions table. these specifications are eas- ily met by many of the dual n-channel mosfets now available in 8-pin so packages. table 11 lists suggested values for the external resistors and capacitors used in the typical operating circuit . r ix lamp rms 78 1 2 / () = dual-channel automotive ccfl controller 28 ____________________________________________________________________ xxxxxxxx 101 0 a 0 0 a 1 0 communications key write a single byte 8-bits address or data white boxes indicate the master is controlling sda notes 2) the first byte sent after a start condition is always the slave address followed by the read/write bit. shaded boxes indicate the slave is controlling sda start ack not ack s sa a a p data memory address 101 0 a 0 0 a 1 0 101 0 a 0 1 a 1 0 read a single byte sa asr an p data memory address a pn sr stop repeated start 1) all bytes are sent most significant bit first. figure 11. i 2 c communications examples
ds3882 dual-channel automotive ccfl controller ____________________________________________________________________ 29 table 10. transformer specifications (as used in the typical operating circuit ) parameter conditions min typ max units turns ratio (secondary/primary) (notes 1, 2, 3) 40 frequency 40 80 khz output power 6w output current 58ma primary dcr center tap to one end 200 m secondary dcr 500 primary leakage 12 ? secondary leakage 185 mh primary inductance 70 ? secondary inductance 500 mh 100ms minimum 2000 secondary output voltage continuous 1000 v rms note 1: primary should be bifilar wound with center tap connection. note 2: turns ratio is defined as secondary winding divided by the sum of both primary windings. note 3: 40:1 is the nominal turns ratio for driving a 438mm x 2.2mm lamp with a 12v supply. refer to application note 3375 for more information. table 11. resistor and capacitor selection guide designator qty value tolerance (%) at +25? temperature coefficient notes r5, r6 1 10k 1 r3, r4 1 12.5k to 105k 1 see the setting the svm threshold voltage section. r9 1 20k to 40k 1 153ppm/? 2% or less total tolerance. see the lamp frequency configuration section to determine value. r10 1 18k to 45k 1 153ppm/? 2% or less total tolerance. see the lamp frequency configuration section to determine value. r1 1 4.7k 5 any grade r2 1 4.7k 5 any grade r11 1 4.7k 5 any grade r7, r8 1/chan 140 1 see the setting the rms lamp current section. c6, c8 1/chan 100nf 10 x7r c ap aci tor val ue w i l l al so affect lc m b i as vol tag e d ur i ng p ow er - up . a l ar g er cap aci tor m ay cause a l ong er ti m e for v d c b to r each i ts nor m al op er ati ng l evel . c2 1/chan 10pf 5 1000ppm/c 2kv to 4kv breakdown voltage required. c3 1/chan 27nf 5 x7r c ap aci tor val ue w i l l al so affect lc m b i as vol tag e d ur i ng p ow er - up . a l ar g er cap aci tor m ay cause a l ong er ti m e for v d c b to r each i ts nor m al op er ati ng l evel . c1 1/chan 33? 20 any grade c7 2/ds3882 0.1? 10 x7r place close to v cc and gnd on ds3882.
ds3882 dual-channel automotive ccfl controller 30 ____________________________________________________________________ inverter supply voltage (v inv ) (8v to 16v) ga1 lamp current monitor ccfl lamp gb1 ovd1 v cc v cc v cc v cc bright svmh lamp brightness transformer dual power mosfet device supply voltage (5v 5%) overvoltage detection lcm1 gnd lamp frequency input/output lsync scl sda i 2 c configuration and control port fault psync dpwm signal input/output losc posc lco pdn lamp on/off lamp current overdrive enable svml a0 a1 hardware control step lamp frequency step gnd_s r1 r2 r7 r9 r10 c2 c3 c7 r11 c8 r3 r4 r5 r6 c1 ga2 lamp current monitor ccfl lamp gb2 ovd2 transformer dual power mosfet overvoltage detection lcm2 r8 c4 c5 c6 ds3882 typical operating circuit power-supply decoupling to achieve best results, it is highly recommended that a decoupling capacitor is used on the ic power-supply pin. typical values of decoupling capacitors are 0.01? or 0.1?. use a high-quality, ceramic, surface- mount capacitor, and mount it as close as possible to the v cc and gnd pins of the ic to minimize lead inductance. chip information substrate connected to ground package information for the latest package outline information and land patterns, go to www.maxim-ic.com/packages . note that a ?? ?? or ??in the package code indicates rohs status only. package drawings may show a different suffix character, but the drawing pertains to the package regardless of rohs status. package type package code outline no. land pattern no. 28 tssop (173 mils) u28+2 21-0066 90-0171
ds3882 dual-channel automotive ccfl controller maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a maxim product. no circu it patent licenses are implied. maxim reserves the right to change the circuitry and specifications without notice at any time. maxim integrated products, 120 san gabriel drive, sunnyvale, ca 94086 408-737-7600 ____________________ 31 2010 maxim integrated products maxim is a registered trademark of maxim integrated products, inc. is a registered trademark of maxim integrated products, inc. revision history revision number revision date description pages changed 0 3/06 initial release 1 8/07 updated table 5b to change bit 7 lst[1:0] at 1:1 from 131,072 lamp frequency cycles to reserved 21 2 12/10 updated the ordering information table part numbers; added the continuous power dissipation numbers for a single-layer board and the lead and soldering temperature information to the absolute maximum ratings section; added the package information table 1, 2, 30

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